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description designed for pulse width modulated (pwm) control of dc motors, the A4952 and a4953 are capable of peak output currents to 2 a and operating voltages to 40 v. input terminals are provided for use in controlling the speed and direction of a dc motor with externally applied pwm control signals. internal synchronous rectification control circuitry is provided to lower power dissipation during pwm operation. internal circuit protection includes overcurrent protection, motor lead short to ground or supply, thermal shutdown with hysteresis, undervoltage monitoring of v bb , and crossover- current protection. the A4952 is provided in a low-profile 10-pin msop package (suffix ly) and the a4953 is provided in a low-profile 8-pin soicn package (suffix lj). both packages have an exposed thermal pad, and are lead (pb) free, with 100% matte tin leadframe plating. A4952-ds, rev. 2 features and benefits ? low r ds(on) outputs ? overcurrent protection (ocp) ? motor short protection ? motor lead short to ground protection ? motor lead short to battery protection ? low power standby mode ? adjustable pwm current limit ? synchronous rectification ? internal undervoltage lockout (uvlo) ? crossover-current protection ? fault output (A4952 only) ? selectable retry (A4952 only) full-bridge dmos pwm motor drivers functional block diagram A4952 and a4953 control logic lss out1 out2 vbb in1 in2 charge pump osc disable load supply uvlo vref 7v v int A4952 only gnd (optional) tsd 10 rtry fltn A4952 only packages: not to scale 8-pin soicn with exposed thermal pad (lj package) 10-pin msop with exposed thermal pad (ly package)
full-bridge dmos pwm motor drivers A4952 and a4953 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com terminal list table name number function A4952 a4953 fltn 1 ? fault output, active low gnd 10 1 ground in1 4 3 logic input 1 in2 3 2 logic input 2 lss 8 7 power return ? sense resistor connection out1 7 6 dmos full bridge output 1 out2 9 8 dmos full bridge output 2 pad ? ? exposed pad for enhanced thermal dissipation rtry 2 ? logic input vbb 6 5 load supply voltage vref 5 4 analog input pin-out diagrams absolute maximum ratings characteristic symbol notes rating unit load supply voltage v bb 40 v logic i/o voltage range v in ?0.3 to 6 v fltn sink current i fltn 10 ma v ref input voltage range v ref ?0.3 to 6 v sense voltage (lss pin) v s ?0.5 to 0.5 v motor outputs voltage v out ?2 to 42 v output current i out duty cycle = 100% 2 a transient output current i out t w < 500 ns 6 a operating temperature range t a temperature range e ?40 to 85 c maximum junction temperature t j (max) 150 c storage temperature range t stg ?55 to 150 c selection guide part number packing A4952elytr-t 4000 pieces per 13-in. reel a4953eljtr-t 3000 pieces per 13-in. reel thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja lj package, on 4-layer pcb based on jedec standard 35 oc/w lj package, on 2-layer pcb with 0.8 in 2 . 2-oz. copper each side 62 oc/w ly package, on 4-layer pcb based on jedec standard 48 oc/w ly package, (estimate) on 2-layer pcb with 1 in 2 . 2-oz. copper each side 60 oc/w *additional thermal information available on the allegro website. 8 7 6 5 1 2 3 4 out2 lss out1 vbb gnd in2 in1 vref pad fltn rtry in2 in1 vref gnd out2 lss out1 vbb 1 2 3 4 5 10 9 8 7 6 pad lj package (a4953) ly package (A4952)
full-bridge dmos pwm motor drivers A4952 and a4953 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics valid at t j = 25c, unless otherwise specified characteristics symbol test conditions min. typ. max. unit general load supply voltage range v bb 8 ? 40 v r ds(on) sink + source total r ds(on) i out = |1.5 a|, t j = 25c ? 0.8 1.0 i out = |1.5 a|, t j = 125c ? 1.3 1.6 load supply current i bb f pwm < 30 khz ? 10 ? ma low power standby mode ? ? 10 a body diode forward voltage v f source diode, i f = ?1.5 a ? ? 1.5 v sink diode, i f = 1.5 a ? ? 1.5 v logic i/o inputs logic input voltage range v in(1) inx pins 2.0 ? ? v v in(0) inx pins ? ? 0.8 v v in(standby) inx pins, low power standby mode ? ? 0.4 v logic input pull-down resistance rr r logic(pd) v in = 0 v = in1 = in2 ? 50 ? k logic input current i in(1) inx pins, v in = 2.0 v ? 40 100 a i in(0 ) inx pins, v in = 0.8 v ? 16 40 a input hysteresis v hys ? 250 550 mv logic i/o inputs (A4952 only) retry input voltage v rtry rtry pin = valid ? ? 200 mv retry overcurrent protection pullup voltage v rtry(oc) rtry pin = open ? 3 ? v retry short circuit current i rtry rtry pin = gnd ? 10 ? a fault output voltage v rst fltn pin, i out = 1 ma ? ? 0.5 v fault output leakage current i lk fltn pin, no fault, pull-up to 5 v ? ? 1 a timing crossover delay t cod 50 400 500 ns v ref input voltage range v ref 0?5v current gain a v v ref / i ss , v ref = 5 v 9.5 ? 10.5 v/v v ref / i ss , v ref = 2.5 v 9.0 ? 10.0 v/v v ref / i ss , v ref = 1 v 8.0 ? 10.0 v/v blank time t blank 234 s constant off-time t off 16 25 34 s standby timer t st in1 = in2 < v in(standby) ? 1 1.5 ms power-up delay t pu ??30 s protection circuits uvlo enable threshold v bbuvlo v bb increasing 7 7.5 7.95 v uvlo hysteresis v bbuvlohys ? 500 ? mv thermal shutdown temperature t jtsd temperature increasing ? 160 ? c thermal shutdown hysteresis t tsdhys recovery = t jtsd ? t tsdhys ?20?c
full-bridge dmos pwm motor drivers A4952 and a4953 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance pwm control timing diagram pwm control truth table in1 in2 10 v s > v ref out1 out2 function 0 1 false l h reverse 1 0 false h l forward 0 1 true h/l l chop (mixed decay), reverse 1 0 true l h/l chop (mixed decay), forward 1 1 false l l brake (slow decay) 0 0 false z z coast, enters low power standby mode after 1 ms note: z indicates high impedance. reverse/ fast decay reverse/ slow decay forward/ fast decay forward/ slow decay gnd gnd +i reg 0 a -i reg in1 in2 i out(x) v in(1) v in(1)
full-bridge dmos pwm motor drivers A4952 and a4953 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description device operation the A4952 and a4953 are designed to operate dc motors. the output drivers are all low-r ds(on) , n-channel dmos drivers that feature internal synchronous rectification to reduce power dissipation. the current in the output full bridge is regulated with fixed off-time pulse width modulated (pwm) control circuitry. the in1 and in2 inputs allow two-wire control for the bridge. protection circuitry includes internal thermal shutdown, and pro- tection against shorted loads, or against output shorts to ground or supply. undervoltage lockout prevents damage by keeping the outputs off until the driver has enough voltage to operate nor- mally. standby mode low power standby mode is activated when both input (inx) pins are low for longer than 1 ms. low power standby mode disables most of the internal circuitry, including the charge pump and the regulator. when the A4952/a4953 is coming out of standby mode, the charge pump should be allowed to reach its regulated voltage (a maximum delay of 200 s) before any pwm commands are issued to the device. internal pwm current control initially, a diagonal pair of source and sink fet outputs are enabled and current flows through the motor winding and the optional external current sense resistor, r s . when the voltage across r s equals the comparator trip value, then the current sense comparator resets the pwm latch. the latch then turns off the sink and source fets (mixed decay mode). v ref the maximum value of current limiting is set by the selection of r sx and the voltage at the vref pin. the transconductance func- tion is approximated by the maximum value of current limiting, i tripmax (a), which is set by: i tripmax = a v r s v ref where v ref is the input voltage on the vref pin (v) and r s is the resistance of the sense resistor ( ) on the lss terminal. overcurrent protection in the A4952, a current monitor will protect the ic from damage due to output shorts. the internal overcurrent protection (ocp) has the following features: ? fault output (fltn pin). if a short is detected, the open drain fltn output signal goes low. ? retry input (rtry pin). sets the action taken by the ic to re- spond to an ocp fault. if the rtry pin is tied to gnd, then the outputs will be turned-on again after a 2-ms timeout, to check if a fault condition remains. if the rtry pin is left open, then the fault will be latched, and the ic will disable the outputs. the fault latch can only be cleared by coming out of low power standby mode or by cycling the power to vbb. note: the a4953 overcurrent protection behaves in the same manner but the fault is latched and can only be reset by putting the device into standby mode or by cycling the power to vbb. during ocp events, absolute maximum ratings may be exceeded for a short period of time before the device latches. shutdown if the die temperature increases to approximately 160c, the full bridge outputs will be disabled until the internal temperature falls below a hysteresis, t tsdhys , of 20c. internal uvlo is present on vbb to prevent the output drivers from turning-on below the uvlo threshold. braking the braking function is implemented by driving the device in slow decay mode, which is done by applying a logic high to both inputs, after a bridge-enable chop command (see pwm control truth table). because it is possible to drive current in both direc- tions through the dmos switches, this configuration effectively shorts-out the motor-generated bemf, as long as the chop com- mand is asserted. the maximum current can be approximated by v bemf / r l . care should be taken to ensure that the maximum ratings of the device are not exceeded in worse case braking situ- ations: high speed and high-inertia loads.
full-bridge dmos pwm motor drivers A4952 and a4953 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com synchronous rectification when a pwm off-cycle is triggered by an internal fixed off-time cycle, load current will recirculate. the A4952/a4953 synchro- nous rectification feature turns-on the appropriate dmosfets during the current decay, and effectively shorts out the body diodes with the low r ds(on) driver. this significantly lowers power dissipation. when a zero current level is detected, syn- chronous rectification is turned off to prevent reversal of the load current. mixed decay operation the bridges operate in mixed decay mode. referring to the lower panel of the figure below, as the trip point is reached, the device goes into fast decay mode for 50% of the fixed off-time period. after this fast decay portion the device switches to slow decay mode for the remainder of the off-time. during transitions from fast decay to slow decay, the drivers are forced off for the crossover delay, t cod . this feature is added to prevent shoot- through in the bridge. during this ?dead time? portion, synchro- nous rectification is not active, and the device operates in fast decay and slow decay only. mixed decay mode operation v phase i out i out + ? 0 see enlargement a enlargement a t cod t cod t cod fixed off-time, t off = 25 s fast decay slow decay i trip 0.50 t off 0.50 t off
full-bridge dmos pwm motor drivers A4952 and a4953 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information sense pin (lss) in order to use pwm current control, a low-value resistor is placed between the lss pin and ground for current sensing pur- poses. to minimize ground-trace ir drops in sensing the output current level, the current sensing resistor should have an indepen- dent ground return to the star ground point. this trace should be as short as possible. for low-value sense resistors, the ir drops in the pcb can be significant, and should be taken into account. when selecting a value for the sense resistor be sure not to exceed the maximum voltage on the lss pin of 500 mv at maximum load. during overcurrent events, this rating may be exceeded for short durations. ground a star ground should be located as close to the A4952/ a4953 as possible. the copper ground plane directly under the exposed thermal pad of the device makes a good location for the star ground point. the exposed pad can be connected to ground for this purpose. layout the pcb should have a thick ground plane. for optimum electri- cal and thermal performance, the A4952/a4953 must be soldered directly onto the board. on the underside of the A4952/a4953 package is an exposed pad, which provides a path for enhanced thermal dissipation. the thermal pad must be soldered directly to an exposed surface on the pcb in order to achieve optimal ther- mal conduction. thermal vias are used to transfer heat to other layers of the pcb. the load supply pin, vbb, should be decoupled with an electro- lytic capacitor (typically 100 f) in parallel with a lower valued ceramic capacitor placed as close as practicable to the device. gnd rs gnd gnd gnd c1 bulk capacitance vbb out2 out1 c2 v bb 1 pad A4952 c1 c2 out2 lss out1 vbb fltn rtry in2 in1 vref gnd r s pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz. solder A4952 bill of materials item reference value units description 1rs 0.25 (for v ref = 5 v, i out = 2 a) 2512, 1 w, 1% or better, carbon film chip resistor 2 c1 0.22 f x5r minimum, 50 v or greater 3 c2 100 f electrolytic, 50 v or greater layout for the A4952 (ly package)
full-bridge dmos pwm motor drivers A4952 and a4953 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com gnd rs gnd gnd gnd c1 bulk capacitance vbb out2 out1 c2 v bb 1 pad a4953 c1 c2 out2 lss out1 vbb in2 in1 vref gnd r s pcb thermal vias trace (2 oz.) signal (1 oz.) ground (1 oz.) thermal (2 oz.) solder a4953 bill of materials item reference value units description 1rs 0.25 (for v ref = 5 v, i out = 2 a) 2512, 1 w, 1% or better, carbon film chip resistor 2 c1 0.22 f x5r minimum, 50 v or greater 3 c2 100 f electrolytic, 50 v or greater layout for the a4953 (lj package)
full-bridge dmos pwm motor drivers A4952 and a4953 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lj, 8-pin soicn with exposed thermal pad 3.30 2 1 8 reference land pattern layout (reference ipc7351 soic127p600x175-9am); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c 1.27 5.60 2.41 1.75 0.65 2.41 nom 3.30 nom c seating plane 1.27 bsc gauge plane seating plane a terminal #1 mark area b c b 2 1 8 c seating plane c 0.10 8x 0.25 bsc 1.04 ref 1.70 max for reference only; not for tooling use (reference ms-012ba) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown 4.90 0.10 3.90 0.10 6.00 0.20 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 8 0 exposed thermal pad (bottom surface); dimensions may vary with device a branded face
full-bridge dmos pwm motor drivers A4952 and a4953 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package ly, 10-pin msop with exposed thermal pad terminal #1 mark area a gauge plane seating plane 0.86 0.05 seating plane 0.50 ref 0.25 2 1 10 2 1 10 a b c c 0.53 0.10 0.15 0.05 0.05 0.15 0 to 6 3.00 0.10 3.00 0.10 4.88 0.20 1.73 4.60 1.98 1.98 min 1.73 2 1 10 1 0.30 0.50 1.65 0.27 0.18 for reference only; not for tooling use (reference jedec mo-187ba-t) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b exposed thermal pad (bottom surface) reference land pattern layout (reference ipc7351 sop50p490x110-11m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5)
full-bridge dmos pwm motor drivers A4952 and a4953 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2010-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision rev. 2 august 6, 2012 update pwm table

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